The present invention relates to a check pattern to be used for opening examination of via-holes configured on a semiconductor substrate having multi-layer wirings.
In Japanese patent application laid open as a Provisional Publication 12531/'92, there is disclosed a check pattern to be used for examining whether via-holes are correctly configured on a semiconductor substrate or not. FIG. 11 is a cross section schematically illustrating the prior check pattern disclosed in the aforesaid patent application.
Referring to FIG. 11, a prior check pattern comprises more than one wiring 102 configured neighboring each other on a lower layer provided on a semiconductor substrate 101, an inter-layer insulation film 103 configured on the semiconductor substrate 101 covering the wirings 102, a resist pattern 104 configured on the inter-layer insulation film 103, and a via-hole 105, a bottom thereof having a step 105a traversing the wirings 102 and the inter-layer insulation film 103 between the wirings 102.
By surveying the via-hole 105 with a scanning electron-microscope, it is confirmed that the via-hole 105 is correctly configured so that the bottom of the via-hole 105 extends to the surface of the wirings 102, when a contrast between a light part owing to the wirings 102 and a dark part owing to the step 105a is observed.
Thus, whether the via-hole 105 is correctly configured or not can be discriminated by whether a contrast is observed or not when the via-hole 105 is surveyed by a scanning electron-microscope.
FIG. 12 is a cross section illustrating another example of a prior check pattern, wherein more than one wirings 202 configured neighboring each other on a lower layer provided on a semiconductor substrate 201, an inter-layer insulation film 203 configured on the semiconductor substrate 201 covering the wirings 202, a resist pattern 204 configured on the inter-layer insulation film 203, and a via-hole 205, a bottom thereof having a step 205a traversing at least one of the wirings 202 and the inter-layer insulation film 203 between the wirings 202 are depicted.
In the check pattern of FIG. 12, whether the via-hole 205 is correctly configured or not can be discriminated by whether a contrast can be observed or not when the via-hole is surveyed with a scanning electron-microscope, as well as in the check pattern of FIG. 11, on condition the via-hole 205 is so configured that the bottom thereof may traverse both of at least one of the wirings 202 and the inter-layer insulation film 203 between the wirings 202.
Therefore, in the prior art, the diameter of the via-hole is preferably designed to be longer than the spacing between the wirings.
However, as integration of semiconductor circuit becomes higher and higher recently, standardization concerning standards for semiconductor devices such as wiring widths and spacings is being promulgated.
For example, in p. 98 of a publication of SIA (Semiconductor Industry Association) entitled "The National Technology Roadmap for Semiconductors", there is described a "table 22: Interconnect Design Ground Rules and Assumptions" showing design rules of aluminum wirings, wherein wiring width, wiring spacing and via-hole size of 0.35 .mu.m-rule devices are defined to be 0.4 .mu.m, 0.6 .mu.m and 0.4 .mu.m, respectively. Furthermore, it is assumed according to the document that the wiring width, the wiring spacing and the via-hole size of future 0.1 .mu.m-rule devices will be defined as 0.11 .mu.m, 0.16 .mu.m and 0.11 .mu.m, respectively.
Hence, according to the above standard, the bottom of the via-hole of the check pattern for the opening examination of via-holes can not be designed to traverse two wirings as in the prior check pattern of FIG. 11.
Further, it also will become very difficult to configure the bottom of the via-hole of the check pattern to traverse both of at least one of the wirings and the inter-layer insulation film between them such as in the prior check pattern of FIG. 12. It is because the via-hole size becomes very fine and there is a limit in preciseness of positioning for configuring the via-hole, and so, the via-hole bottom may not traverse both the wiring or the inter-layer insulation film. Even if the via-hole bottom can be configured to traverse both of the wiring and the inter-layer insulation film, the relative proportion of either of them may often become far smaller than the other. In such case, no contrast may be observed when the via-hole is surveyed with the scanning electron-microscope, and consequently, the via-hole may be regarded not to be configured sufficiently even if it is made correctly.
Therefore, extremely high-precision positioning will become necessary for configuring the via-hole, in order to prevent mal-configuration of via-holes according to a prior check pattern.
Furthermore, there is a problem that a mal-configured via-hole may be regarded to be made correctly when electron beam of the scanning electron-microscope surveying the via-hole is not vertically incident to the via-hole bottom, by mistaking a shadow of the electron beam as the dark part owing to the inter-layer insulation film.
As to the reason the electron beam is not incident vertically to the via-hole bottom, there can be considered cases such as the electron gun of the scanning electron-microscope is not adjusted sufficiently or warp is found in the semiconductor substrate. The warp of the semiconductor substrate is easily caused in a wiring patterning process because high-speed thermo-processes such as the lamp-anneal method have been frequently performed in the substrate preparing procedure before the wiring patterning process.
Furthermore, when the aspect-ratio (ratio of depth to width) of the via-hole becomes comparatively large, no incident election beam may reach the bottom of the via-hole, resulting in further inconvenience of the electron beam not incident vertically to the via-hole bottom. In this connection, the aspect-ratio of the via-hole is defined, in the above document, as 2.5 to 4.5 for the 0.35 .mu.m-rule devices, and assumed to become 5.2 to 9 for the future 0.1 .mu.m-rule devices.
In either case, it is needed to re-adjust the electron gun of the scanning electron-microscope when the electron beam is not incident vertically to the via-hole bottom, and the necessity of the re-adjustment operation has been one of the causes to degrade efficiency of the via-hole opening examination.